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winbond integrated media reader W83L518D datasheet
W83L518D data sheet revision history pages dates version version on web main contents 1 02/jul. 1.0 1.0 1 st release 2 3 4 5 6 7 8 please note that all data and specifications are subject to change without notice. al l the trademarks of products and companies mentioned in this data sheet belong to their respective owners. life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these product s can reasonably be expected to result in personal injury. winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify winbond for any damages resulting from such improper use or sales .
content 1 general description ................................ ................................ ................................ ....... 1 2 functions ................................ ................................ ................................ ........................... 2 2.1 g eneral ................................ ................................ ................................ ................................ ... 2 2.2 s mart c ard i nterface ................................ ................................ ................................ .............. 2 2.3 m emory s tick i nterface ................................ ................................ ................................ ............ 2 2.4 sd m emory c ard i nterface ................................ ................................ ................................ ....... 2 2.5 p ackage ................................ ................................ ................................ ................................ .. 2 3 pin configuration fo r W83L518D ................................ ................................ ................... 3 4 pin description ................................ ................................ ................................ ................. 4 4.1 b us i nterface ................................ ................................ ................................ ........................... 4 4.2 s mart c ard i nterface p ins ................................ ................................ ................................ ....... 5 4.3 m emory s tick i nterface /sd m emory i n terface p ins ................................ ................................ .... 6 4.4 g eneral - p urpose i/o p ins ................................ ................................ ................................ ......... 7 4.5 c rystal and p ower p ins ................................ ................................ ................................ .......... 7 5 general - purpose i/o ports (g pio) ................................ ................................ ................. 8 6 configuration regist er ................................ ................................ ............................... 10 6.1 p lug and p lay c onfiguration ................................ ................................ ................................ . 10 6.2 c ompatible p n p ................................ ................................ ................................ ...................... 10 6.2.1 extended function register ................................ ................................ ............................... 10 6.2.2 extended functions enable register (efer) ................................ ................................ ...... 11 6.2.3 extended function index register (efir), extended function data register (efdr) .............. 11 6.3 c onfiguration s equence ................................ ................................ ................................ ......... 11 6.3.1 software programming example ................................ ................................ .......................... 12 6.4 g lobal r egisters ................................ ................................ ................................ ................... 12 6.5 l ogical d evice 0 (s mart c ard i n terface ) ................................ ................................ ................. 15 6.6 l ogical d evice 1 (m emory s tick i nterface ) ................................ ................................ ............... 15 6.7 l ogical d evice 2 (gpio) ................................ ................................ ................................ .......... 16 6.8 l ogical d evice 3 (sd m emory i nterface ) ................................ ................................ .................. 18 7 ordering instruction ................................ ................................ ................................ .... 19 8 how to read the top marking ................................ ................................ ..................... 19 9 package drawing and dimensions ................................ ................................ .............. 20 10 the W83L518D schemat ic ................................ ................................ ............................. 22
W83L518D the trademarks and intellectual property rights of memory stick belong to sony corporation publication release date: jul . 2002 the trademarks and intellectual property rights of sd belong to sd group revision 1.0 all trademarks and brand names belong to their respective owners 1 1 general description W83L518D is winbond's innovative so lution to a new class of storage devices for ia noetebook, desktop pc and pc system - related products. it incorporates a security application: smart card interface and two most promising compact storage interfaces: memory stick interface, and sd memory car d/multimedia card interface in it era. to cater boundless it implementation possibilities, W83L518D can be configured to interface with host through lpc bus. base on the lpc interface, one smart card interface port and two flash memory interfaces - memory stick and sd memory ports are provided. the kind of versatility allows user to design very cost - effective products in a very flexible way. the whole chip of W83L518D operates at voltage level of 3.3 v except smart card interface port's i/o pins that are at 5 v to be compatible with mainstream smart card implementations. advanced power management feature further optimizes power consumption whether in operation or in power down mode. W83L518D comes as a 48 - pin lqfp streamline package. combining with powerfu l functions, effective power management, and versatile configurability, this integrated media reader offers a perfect approach for design of storage device of it products. the trademarks and intellectual property rights of memory stick belong to sony corpo ration. information check: http://www.memorystick.org/ the trademarks and intellectual property rights of secure digital belong to sd group. information check: http://www.sdc ard.org/
W83L518D the trademarks and intellectual property rights of memory stick belong to sony corporation publication release date: jul . 2002 the trademarks and intellectual property rights of sd belong to sd group revision 1.0 all trademarks and brand names belong to their respective owners 2 2 functions 2.1 general q lpc bus is compliant with lpc spec. 1.01 q lpc bus supports ldrq# (lpc dma), serirq (serial irq) q programmable configuration settings q 48 mhz crystal inputs q pciclk of 33 mhz is needed for lpc bus configuration 2.2 smart card interfac e q iso - 7816 compliant q pc/sc t=0, t=1 compliant q 16 - byte transmitter fifo and 16 - byte receiver fifo q fifo threshold interrupt to optimize system performance q programmable transmission clock frequency q versatile baud rate configuration q uart - like register file str ucture q general - purpose c4, c8 channels 2.3 memory stick interface q memory stick standard format specifications ver. 1.3 compliant q support interrupt polling transmission q support fifo threshold interrupt to optimize system performance q automatic clock halt to pre vent underrun/overrun q 16 mhz interface clock 2.4 sd memory card interface q sd memory card specifications: part 1 physical layer specification version 1.0 compliant q support interrupt polling transmission q support fifo threshold interrupt to leverage system perfo rmance q 24 mhz interface clock 2.5 package q 48 - pin lqfp
W83L518D the trademarks and intellectual property rights of memory stick belong to sony corporation publication release date: jul . 2002 the trademarks and intellectual property rights of sd belong to sd group revision 1.0 all trademarks and brand names belong to their respective owners 3 3 pin configuration fo r W83L518D W83L518D pciclk ldrq# lframe# reset# pme# vss gp17 gp16 gp15 gp14 gp13 gp12 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 sdpwr#/gp21 sdled/gp20 scc4 scc8 msled mspwr# vss msclk ms1 ms2 ms3 ms4 sdclk /gp22 sd1 /gp23 sd2 /gp24 vdd3v sd3 /gp25 sd4 /gp26 sd5 /gp27 lad3 lad2 lad1 lad0 serirq ms 5 xin xout scrst# scio scclk scpsnt scpwr# scled vdd gp10 gp11 24 23 22 21 20 19 18 17 16 15 14 13 37 38 39 40 41 42 43 44 45 46 47 48
W83L518D the trademarks and intellectual property rights of memory stick belong to sony corporation publication release date: jul . 2002 the trademarks and intellectual property rights of sd belong to sd group revision 1.0 all trademarks and brand names belong to their respective owners 4 4 pin description note: in t - 5v ttl level input pin in tp3 - 3.3v ttl level input pin in ts - 5v ttl level schmitt - trigger input pin in tsp3 - 3. 3v ttl level schmitt - trigger input pin i/o 12t - 5v ttl level bi - directional pin with 12 ma drive - sink capability i/o 24t - 5v ttl level bi - directional pin with 24 ma drive - sink capability i/o 16 tp3 - 3.3v ttl level bi - directional pin with 16 ma drive - sink capability o 2 - 5v output pin with 2 ma drive - sink capability o 12 - 5v output pin with 12 ma drive - sink capability o 16 p3 - 3.3v output pin with 16 ma drive - sink capability od 12p3 - 3.3v open - drain output pin with 12 ma sink capability. 4.1 bus interface s ymbol pin i/o function pme# 5 od 12p3 active - low pme event. reset# 4 in tsp3 active - low system reset signal. lframe# 3 in tsp3 active - low signal indicates start of a new lpc frame or termination of a premature frame. ldrq# 2 o 16 p3 encoded dma request si gnal. pciclk 1 in tsp3 pci clock input of 33 mhz. serirq 48 i/o 16 tp3 serial irq input/output. lad0 47 i/o 16 tp3 this signal combining with other ladx signals communicate address, control, and data information over the lpc bus between a host and a perip heral. lad1 46 i/o 16 tp3 this signal combining with other ladx signals communicate address, control, and data information over the lpc bus between a host and a peripheral. lad2 45 i/o 16 tp3 this signal combining with other ladx signals communicate address, control, and data information over the lpc bus between a host and a peripheral. lad3 44 i/o 16 tp3 this signal combining with other ladx signals communicate address, control, and data information over the lpc bus between a host and peripherals.
W83L518D the trademarks and intellectual property rights of memory stick belong to sony corporation publication release date: jul . 2002 the trademarks and intellectual property rights of sd belong to sd group revision 1.0 all trademarks and brand names belong to their respective owners 5 4.2 smart card interface pins symbol pin i/o function scc4 34 i/o 16 tp3 smart card interface general purpose i/o channel for connector pin c4 on a card. scc8 33 i/o 16 tp3 smart card interface general purpose i/o channel for connector pin c8 on a card. scl ed 16 o 24 this pin outputs an oscillating clock signal of various frequencies depending on traffic of primary smart card interface. scpwr# 17 o 24 smart card interface power control signal. scpsnt 18 in ts smart card interface card present detection schmit t - trigger input. scclk 19 o 2 smart card interface clock output. scio 20 i/o 12t smart card interface data i/o channel. scrst# 21 o 12 smart card interface reset output.
W83L518D the trademarks and intellectual property rights of memory stick belong to sony corporation publication release date: jul . 2002 the trademarks and intellectual property rights of sd belong to sd group revision 1.0 all trademarks and brand names belong to their respective owners 6 4.3 memory stick interface/sd memory interface pins symbol pin i/o function msled 32 o 1 6 p3 memory stick function - this pin outputs an oscillating clock signal of various frequencies depending on traffic of the memory stick interface. mspwr# 31 o 16 p3 memory stick function - this pin is power control signal for the memory stick interface. msclk 29 o 16 p3 memory stick function - this pin is sclk for the memory stick interface. ms1 28 o 16 p3 memory stick interface pin. ms2 27 i/o 16 tp3 memory stick interface pin. ms3 26 --- memory stick interface pin. ms4 25 in tsp3 memory stick interface pin. ms5 24 --- memory stick interface pin. sd5 43 i/o 16 tp3 sd interface pin. sd interface pin. 42 i/o 16 tp3 sd interface pin. sd interface pin. 41 i/o 16 tp3 sd interface pin. sd interface pin. 39 i/o 16 tp3 sd interface pin. sd interface pin. 38 i/o 16 tp 3 sd interface pin. sdclk 37 o 16 p3 sd function - this pin is clk for the sd memory card interface. sdpwr# 36 o 16 p3 sd function - this pin is power control signal for the sd memory card interface. sdled 35 o 16 p3 sd function - this pin outputs an oscillat ing clock signal of various frequencies depending on traffic of the sd memory card interface. card_detect 13 in t function as an alternative card detection input for the sd memory interface.
W83L518D the trademarks and intellectual property rights of memory stick belong to sony corporation publication release date: jul . 2002 the trademarks and intellectual property rights of sd belong to sd group revision 1.0 all trademarks and brand names belong to their respective owners 7 4.4 general - purpose i/o pins symbol pin i/o function gp17 7 i/o 12 t general - purpose i/o port 17. gp16 8 i/o 12t general - purpose i/o port 16. gp15 9 i/o 12t general - purpose i/o port 15. gp14 10 i/o 12t general - purpose i/o port 14. gp13 11 i/o 12t general - purpose i/o port 13. gp12 12 i/o 12t general - purpose i/o port 12. g p11 ex_cd 13 i/o 12t general - purpose i/o port 11. external card detedtion pin. the detectable level can be set on bit 2 of cr f0 on logical device 3. gp10 phefras 14 i/o 12t in t general - purpose i/o port 10. this pin also functions as a power - on setting pin whose value is latched on the rising edge of reset# (pin 4) to select configuration ports as 2 e h/2 f h (phefras = 1) or 4 e h/4 f h (phefras = 0). it determines the default value of cr26 bit 6 (hefras). 4.5 crystal and power pins symbol pin function xout, xin 2 2, 23 connected to a 48 mhz crystal and function as the working clock for all the media reader interfaces. vdd3v 40 +3.3v power supply for host interface, memory stick/sd memory interfaces, and internal core. vdd 15 +5v power supply for smart card interf ace i/o pins. vss 6, 30 ground.
W83L518D the trademarks and intellectual property rights of memory stick belong to sony corporation publication release date: jul . 2002 the trademarks and intellectual property rights of sd belong to sd group revision 1.0 all trademarks and brand names belong to their respective owners 8 5 general - purpose i/o ports (g pio) W83L518D supports one group of dedicated general - purpose i/o ports and a multi - functional gpio group, which share the same pines with the sd interface sockets . there are cases when only one socket is needed in a system and pins for the other unused socket are wasted. to provide the most cost - effective solution, W83L518D could be configured to transform these pins into general - purpose i/o ports. the first group (gp10 ~ 17) is configured through the configuration registers crf0 ~ crf2 in logical device 2 and the other group (gp20 ~27) through crf3 ~ f5. users can configure each individual port to be an input or output port by programming respective bit in direction register (crf0/crf3: 0 = output, 1 = input). invert port value by setting inversion register (crf2/crf5: 0 = non - inverse, 1 = inverse). port value is read/written through data register (crf1/crf4). table 5.1 and 5.2 illustrate gpio's assignment. to further facilitate system design, W83L518D allows direct accesses to data register and direction register through i/o ports, whose base address is programmable at cr 60, 61 in logical device 2. detailed configuration is described in logical device 2 of section 6 : configuration re gister. gp10 (pin 14) also functions as a power - on setting pin whose value is latched on the rising edge of reset# (pin 4) to select configuation port addresses. therefore, gp10 is a push - pull i/o port unlike the other gpio ports, which are open - drained i /os to support this power - on setting feature . gp11 (pin 13) could function as a card detection input if selected by sdi to support some mmc cards, which don't offer card detection feature through data3 pin. table 5.1 direction bit 0 = output 1 = input inv ersion bit 0 = non inverse 1 = inverse i/o operation 0 0 basic non - inverting output 0 1 basic inverting output 1 0 basic non - inverting input 1 1 basic inverting input
W83L518D the trademarks and intellectual property rights of memory stick belong to sony corporation publication release date: jul . 2002 the trademarks and intellectual property rights of sd belong to sd group revision 1.0 all trademarks and brand names belong to their respective owners 9 table 5.2 gpio port data register register bit assignm ent gp i/o port bit 0 gp 10 bit 1 gp11 bit 2 gp12 bit 3 gp13 gp1 bit 4 gp14 bit 5 gp15 bit 6 gp16 bit 7 gp17 bit 0 gp20 bit 1 gp21 gp2 bit 2 gp22 bit 3 gp23 bit 4 gp24 bit 5 gp25 bit 6 gp26 bit 7 gp27
W83L518D the trademarks and intellectual property rights of memory stick belong to sony corporation publication release date: jul . 2002 the trademarks and intellectual property rights of sd belong to sd group revision 1.0 all trademarks and brand names belong to their respective owners 10 6 configuration regist er 6.1 plug and play configuratio n W83L518D/w83l519d implement compatible pnp protocol to access configuration registers for setting up different types of configurations. there are four logical devices (logical device 0 to logical device 3 ) in W83L518D/w83l519d which correspond to four m ajor functions: smart card interface (logical device 0), memory stick interface (logical device 1), gpio (logical device 2) and sd memory i nterface (logical device 3) . each logical device has its own configuration registers (cr30 and above). host can acc ess those registers by writing an appropriate logical device number into logical device select register at cr 0 7 first. one set per logical device logical device select 07h 30h 40h feh 3fh logical device control global registers logical device configuration 6.2 compatible pnp 6.2.1 extended function register W83L518D/w83l519d provide two methods to enter extended function m ode (compatible pnp) and access configuration registers dependent on value of hefras (bit 6 of cr26 . the corresponding power - on setting pin is pin 14 ) as follows: hefras address and value 0 write 83h to i/o address 2 e h twice 1 write 83h to i/o address 4 e h twice in compatible pnp, a specific value (83h) must be written twice to the extended function enable register (efer at i/o address 2eh or 4eh). secondly, an index value (02h, 07h - ffh) must be written to the extended function index register (efir, i /o address at 2eh or 4eh which is the same as efer) to
W83L518D the trademarks and intellectual property rights of memory stick belong to sony corporation publication release date: jul . 2002 the trademarks and intellectual property rights of sd belong to sd group revision 1.0 all trademarks and brand names belong to their respective owners 11 identify which configuration register is to be accessed. user can then access the addressed configuration register through the extended function data register (efdr, i/o address at 2fh or 4fh). after programming of the configuration register is completed, another specific value ( 0 aah) should be written to efer to leave extended function mode to prevent inadvertent accesses to those configuration registers. user may write a "1" to bit 5 of cr26 (lockre g) to prevent configuration registers from accidental accesses. 6.2.2 extended functions enable register (efer) after a power - on reset, W83L518D/w83l519d enters the default operation mode. a specific value must be programmed into the extended function enable re gister (efer) so that configuration registers can be accessed. on a pc/at system, its i/o address is 2eh or 4eh (as described in previous section). 6.2.3 extended function index register (efir), extended function data register (efdr) after entering extended fun ction mode, extended function index register (efir) must be written with an index value (02h, 07h - feh) to specify which configuration register is to be accessed through extended function data register (efdr). efir is a write - only register at i/o address 2 eh or 4eh (as described in section 9 .2.1) on a pc/at system and efdr is a read/write register at i/o address 2fh or 4fh. 6.3 configuration sequence to program configuration registers, specific configuration sequence must be followed: (1) write 83h to efer tw ice to enter extended function mode. (2) select logical device select register by writing 07h to efir. (3) select logical device by writing a value to efdr. (4) select control/configuration register by writing its index to efir. (5) access selected control /configuration register through efdr. (6) repeat step 4 ~ 5 as needed. (7) leave extended function mode by writing aah to efer. step 2 and step 3 are not necessary for accessing global register (index 00h to 2fh).
W83L518D the trademarks and intellectual property rights of memory stick belong to sony corporation publication release date: jul . 2002 the trademarks and intellectual property rights of sd belong to sd group revision 1.0 all trademarks and brand names belong to their respective owners 12 6.3.1 software programming example the followi ng example is written in intel 8086 assembly language. efer and efir are assumed to be at 2eh, and efdr is at 2fh. use 4eh/4fh instead of 2eh/2fh if hefras (bit 6 of cr26) is set. ; ------------------------------------------------------------------------- ---------- ; enter extended function mode, interruptible double - write | ; ----------------------------------------------------------------------------------- mov dx, 2eh mov al, 83h out dx, al out dx, al ; ------------------------------------------------ ----------------------------- ; configure logical device 1, configuration register crf0 | ; ----------------------------------------------------------------------------- mov dx, 2eh mov al, 07h out dx, al ; point to logical device number reg. mov dx, 2fh mov al, 01h out dx, al ; select logical device 1 ; mov dx, 2eh mov al, f0h out dx, al ; select crf0 mov dx, 2fh mov al, 3ch out dx, al ; update crf0 with value 3ch ; ------------------------------------------ ; exit extended function mode | ; ------- ----------------------------------- mov dx, 2eh mov al, aah out dx, al 6.4 global registers cr02 (default 00h, write only) bit [7:1]: reserved. bit 0: swrst = 0 normal operation. = 1 software reset. cr07 (default 00h) bit [7:0]: logical device numbe r. cr20 (read only) bit [7:0]: device id number (higher byte). = 71 h
W83L518D the trademarks and intellectual property rights of memory stick belong to sony corporation publication release date: jul . 2002 the trademarks and intellectual property rights of sd belong to sd group revision 1.0 all trademarks and brand names belong to their respective owners 13 cr21 (read only) bit [7:0]: device id number (lower byte) = 1xh (for W83L518D) = 2xh (for w83l519d) x: revision number cr22 (default 8 0h ) bit 7: scpwd = 0 power down smart c ard interface. = 1 no power down. bit 6: mspwd = 0 power down memory stick interface. = 1 no power down. bit 5: sdpwd = 0 power down sd memory card interface. = 1 no power down. bit [ 4 :0] : reserved . cr23 (default 0 0h ) bit 7: pme_en. power ma nagement event enable bit. = 0 pme_l function is disabled. = 1 enable to issue a low pulse on pme_l when a power management event occurs. bit 6: mspme_en. memory stick interface power management event enable bit. = 0 memory stick interface power ma nagement event is disabled. = 1 enable memory stick interface power management event to issue a low pulse on pme_l when pme_en is also enabled. bit 5: sdpme_en. sd memory card interface power management event enable bit. = 0 sd memory card interface power management event is disabled. = 1 enable sd memory card interface power management event to issue a low pulse on pme_l when pme_en is also enabled. bit 4: scpme_en. smart card interface power management event enable bit. = 0 smart card interfac e power management event is disabled. = 1 enable smart card interface power management event to issue a low pulse on pme_l when pme_en is also enabled. bit [ 3 :0] : reserved .
W83L518D the trademarks and intellectual property rights of memory stick belong to sony corporation publication release date: jul . 2002 the trademarks and intellectual property rights of sd belong to sd group revision 1.0 all trademarks and brand names belong to their respective owners 14 cr24 (default 0 0h ) bit 7: reserved. bit 6: mspme_sts. memory stick interface power management event status bit. = 0 no memory stick interface power management event occurs. = 1 memory stick interface power management event occurs. bit 5: sdpme_sts. sd memory card interface power management event status bit. = 0 no sd memory card interface power management event occurs. = 1 sd memory card interface power management event occurs. bit 4: scpme_sts. smart card interface power management event status bit. = 0 no smart card interface power management event occurs. = 1 no sma rt card interface power management event occurs. bit [ 3 :0] : reserved . cr26 (default 4 0 h ) bit 7: reserved bit 6: hefras, extended function register address select. the corresponding power - on setting pin is gp10 (phefras, pin 14). the hefras is defaulte d to "1" if phefras is "0" and is defaulted to "0" if phefras is "1". = 0 extended function registers are at 2eh/2fh. = 1 extended function registers are at 4eh/4fh. bit 5: lockreg = 0 enable accesses of configuration registers. = 1 disable access es of configuration registers. bit [4:0]: reserved cr29 ( default 00 h, only valid in W83L518D ) bit 7: multi - function selection bit for pin 7 ~ 14 = 0 pin 7 ~ 14 function as smart card interface socket b. = 1 pin 7 ~ 14 function as gpio1. bit 6 : multi - function selection bit for pin 35 ~ 43 = 0 pin 35 ~ 43 function as msi/sdi socket b. = 1 pin 35 ~ 43 function as gpio2. bit 5 : multi - function selection bit for pin 32 ~ 31 & pin 29 ~ 24 . = 0 pin 3 2 ~ 31 and pin 29 ~ 24 function as ms a (ms interface card a) . = 1 pin 3 2 ~ 31 and pin 29 ~ 24 function as s da (sd interface card a) . bit 4 : multi - function selection bit for pin 43 ~ 41 & pin 39 ~ 35 . = 0 p in 43 ~ 41 & pin 39 ~ 35 function as ms b (ms interface card b) .
W83L518D the trademarks and intellectual property rights of memory stick belong to sony corporation publication release date: jul . 2002 the trademarks and intellectual property rights of sd belong to sd group revision 1.0 all trademarks and brand names belong to their respective owners 15 = 1 p in 43 ~ 41 & pin 39 ~ 35 f unction as s db (ms interface card b) . bit [ 3 :0]: reserved . 6.5 logical device 0 (smart card interface) cr30 (default 0x00) bit [7:1]: reserved. bit 0: logical device active bit. = 0 logical device is inactive. = 1 activates the logical device. cr60, c r61 (default 0x00, 0x00) these two registers select smart card base address [0x100:0xfff] on 8 - byte boundary. cr70 (default 0x00) bit [7:4]: reserved. bit [3:0]: these bits select irq resource for smart card interface. crf0 (default 0x00) bit 7: irq sh aring control bit. = 0 no irq sharing. = 1 irq sharing. bit 0: scpsnt_pol (smart card present polarity). scpsnt polarity bit. = 0 scpsnt is active high. = 1 scpsnt is active low. 6.6 logical device 1 (memory stick interface) cr30 (default 0x00) bit [7:1]: reserved. bit 0: logical device active bit. = 0 : logical device is inactive. = 1 : activates the logical device. cr60, cr61 (default 0x00, 0x00) these two registers select msi base address [0x100:0xfff] on 8 - byte boundary. cr70 (default 0x00) bit [7:4]: reserved. bit [3:0]: these bits select irq resource for msi.
W83L518D the trademarks and intellectual property rights of memory stick belong to sony corporation publication release date: jul . 2002 the trademarks and intellectual property rights of sd belong to sd group revision 1.0 all trademarks and brand names belong to their respective owners 16 cr74 (default 0x04) bit [7:4]: reserved. bit [3:0]: these bits select drq resource for msi. crf0 (default 0x00) bit [7:5] : reserved. bit 4 : irq polarity co ntrol bit by level mode . = 0 : irq is active high . = 1 : irq is active low . bit 3 : irq polarity control bit by pulse mode . = 0 : irq is active low . = 1 : irq is active high . bit 2 : irq sharing control bit. = 0 : no irq sharing. = 1 : irq sharing. bit 1: ms4 output polarity control bit . 0: ms4 output low. 1: ms4 output high. bit 0: ms4 output enable bit . 0: ms4 output disable. 1: ms4 output enable. 6.7 logical device 2 ( gpio ) cr30 (default 00h ) bit [7: 3 ]: reserved. bit 2 : individual disable/enable bit for gpio2. = 0 gpio2 is disabled if bit 0 is also "0". = 1 gpio2 is enabled . bit 1 : individual disable/enable bit for gpio1. = 0 gpio1 is disabled if bit 0 is a lso "0". = 1 gpio1 is enabled . bit 0: logical device disable/enable bit. = 0 gpio1 and gpio2 are disabled/enabled dependent on bit 1 and 2 respectively .
W83L518D the trademarks and intellectual property rights of memory stick belong to sony corporation publication release date: jul . 2002 the trademarks and intellectual property rights of sd belong to sd group revision 1.0 all trademarks and brand names belong to their respective owners 17 = 1 activates gpio1 and gpio2 . cr60, cr61 ( both d efault 00h ) b ase address configuration register s: programmable at addresses from 0 100 h to 0 ff8 h on 4 - byte boundary. base address + 0 and base address + 1 are for gpio1 as direction register and data register respectively while base address + 2 and base address + 3 are for gpio2 as direction register a nd data register respectively. crf0 (gp10 ~ gp17 direction register. default ffh ) when set to " 1 " , respective gpio port is programmed as an input port. when set to a " 0 " , respective gpio port is programmed as an output port. crf1 (gp10 ~ gp17 data regist er. default 00 h ) if a port is programmed to be an output port, its respective bit can be read/written and output to respective pin . if a port is programmed to be an input port, its respective bit reflects what is on respective pin. crf2 (gp10 ~ gp17 inve rsion register. default 00 h ) when set to " 1 " , respective incoming/outgoing port value is inverted. when set to " 0 " , respective incoming/outgoing port value is the same as in data register. crf 3 (gp 2 0 ~ gp 2 7 direction register. default ffh ) when set to " 1 " , respective gpio port is programmed as an input port. when set to a " 0 " , respective gpio port is programmed as an output port. crf 4 (gp 2 0 ~ gp 2 7 data register. default 00 h ) if a port is programmed to be an output port, its respective bit can be read/w ritten and output to respective pin . if a port is programmed to be an input port, its respective bit reflects what is on respective pin. crf 5 (gp 2 0 ~ gp 2 7 inversion register. default 00 h ) when set to " 1 " , respective incoming/outgoing port value is invert ed. when set to " 0 " , respective incoming/outgoing port value is the same as in data register.
W83L518D the trademarks and intellectual property rights of memory stick belong to sony corporation publication release date: jul . 2002 the trademarks and intellectual property rights of sd belong to sd group revision 1.0 all trademarks and brand names belong to their respective owners 18 6.8 logical device 3 (sd memory interface) cr30 (default 0x00) bit [7:1]: reserved. bit 0: logical device active bit. = 0 logical device is inactive. = 1 activa tes the logical device. cr60, cr61 (default 0x00, 0x00) these two registers select sd card interface base address [0x100:0xfff] on 8 - byte boundary. cr70 (default 0x00) bit [7:4]: reserved. bit [3:0]: these bits select irq resource for sd interface. cr 74 (default 0x00) bit [7:4]: reserved. bit [3:0]: these bits select drq resource for sd interface. crf0 (default 0x01) bit [7:6]: reserved. bit 5: set the output value of the data3 pin when bit4 is setted 1. = 0 the data3 pin will output low. = 1 the data3 pin will output high. bit 4: set the data3 (ms1 or msb1) pin to output pin. = 0 set the data3 pin to bi - direction pin. = 1 set the data3 pin to output pin. bit 3: reserved. bit 2: select the pole of the gp11 card - detect pin. = 0 when det ecting the low signal indicate the card is inserted and high signal indicate the card is extracted. = 1 when detecting the high signal incicate the card is inserted and low signal indicate the card is extracted. bit 1: select gp11 pin to detect card. = 0 don?t use the gp11 pin to detect card. = 1 use the gp11 (scbpwr_l) pin to detect card. bit 0: select data3 pin to detect card. = 0 don?t use the data3 (ms1 or msb1) to detect card. = 1 use the data3 (ms1 or msb1) pin to detect card.
W83L518D the trademarks and intellectual property rights of memory stick belong to sony corporation publication release date: jul . 2002 the trademarks and intellectual property rights of sd belong to sd group revision 1.0 all trademarks and brand names belong to their respective owners 19 crf1 (defau lt 0x01) bit [7:4]: reserved. bit 3: set the irq pole for level mode. = 0 the irq is active high. = 1 the irq is active low. bit 2: set the irq pole for pulse mode. = 0 the irq is active low. = 1 the irq is active high. bit 1: set the irq to le vel mode or pulse mode. = 0 the irq is level mode. = 1 the irq is pulse mode. bit 0: use debounce function for card - detect circuit. = 0 no debouunce. = 1 use debounce function. 7 ordering instruction part no. package remarks W83L518D 48 - pin lq fp 8 how to read the top marking 1st line: winbond logo and the smart@io trademark 2nd line: the chip part number. 3rd line: tracking code 201 g b sb 201 : packages made in ' 02 , week 01 g : assembly house id; o means ose, g m eans gr, ? bsb : ic revision s mart@ io W83L518D 201gbsb
W83L518D the trademarks and intellectual property rights of memory stick belong to sony corporation publication release date: jul . 2002 the trademarks and intellectual property rights of sd belong to sd group revision 1.0 all trademarks and brand names belong to their respective owners 20 9 package drawing and dimensions package - 48 - pin lqfp y seating plane d e e b a2 a1 a 1 12 48 d h e h l1 l c q controlling dimension : millimeters 0.10 0 7 0 0.004 1.00 0.75 0.60 0.45 0.039 0.030 0.024 0.018 9.10 9.00 8.90 0.358 0.354 0.350 0.50 0.20 0.25 1.45 1.40 0.10 0.15 1.35 0.008 0.010 0.057 0.055 0.026 7.10 7.00 6.90 0.280 0.276 0.272 0.004 0.006 0.053 symbol min nom max max nom min dimension in inch dimension in mm a b c d e h d h e l y 0 a a l 1 1 2 e 0.008 0.006 0.15 0.20 7 0.020 0.35 0.65 0.10 0.05 0.002 0.004 0.006 0.15 9.10 9.00 8.90 0.358 0.354 0.350 7.10 7.00 6.90 0.280 0.276 0.272 0.014 37 36 25 24 13
W83L518D the trademarks and intellectual property rights of memory stick belong to sony corporation publication release date: jul . 2002 the trademarks and intellectual property rights of sd belong to sd group revision 1.0 all trademarks and brand names belong to their respective owners 21 headquarters no. 4, creation rd. iii science - based industrial park hsinchu, taiwan tel: 886 - 35 - 770066 fax: 886 - 35 - 789467 www: http://www.winbond.com.tw/ taipei office 9f, no. 480, rueiguang road, neihu district, taipei, 114, taiwa n tel: 886 - 2 - 81777168 fax: 886 - 2 - 87153579 winbond electronics (h.k.) ltd. rm. 803, world trade square, tower ii 123 hoi bun rd., kwun tong kowloon, hong kong tel: 852 - 27516023 - 7 fax: 852 - 27552064 winbond electronics (north america) corp. 2727 n orth first street san jose, california 95134 tel: 1 - 408 - 9436666 fax: 1 - 408 - 9436668 please note that all data and specifications are subject to change without notice. all the trademarks of products and companies mentioned in this data sheet belong to their respective owners . these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify winbond for any damages resulting from such improper use or sale.
W83L518D the trademarks and intellectual property rights of memory stick belong to sony corporation publication release date: jul. .2002 the trademarks and intellectual property rights of sd belong to sd group revision 1.0 all trademarks and brand names belong to their respective owners 22 10 the W83L518D schemat ic 3vcc r22 330 r23 33 1 2 r32 330 1 2 ms[5:1] sdled + c8 1u r15 10 1 2 scapwctl# sd2 r16 4.7k 1 2 sca_vcc y1 48mhz scapwctl# sd[5:1] q6 npn scarst# j3 sc_socket 1 2 3 4 5 6 7 8 9 10 c1 c2 c3 c4 c5 c6 c7 c8 s1 s2 j2 sd_socket 1 2 3 4 5 6 7 8 9 11 10 sd1 sd2 vss1 vdd sdclk vss2 sd3 sd4 sd5 wr_pt ex_cd# sd3 lad3 5vcc rp1 8p4r-4.7k 1 3 5 7 2 4 6 8 hefras sd4 sd1 ms4 q5 npn sd5 5vcc the lc resonance circuit is used to filter base frequency of 3rd overtone crystal. scaclk xout r19 4.7k 1 2 xout power-on strapping for 2e/2f (config. port) 3vcc sc read/write led l1 2.2uh 1 2 c7 0.1u 1 2 r20 330 1 2 d6 led d3 led 3vcc scapsnt sd1 xin r13 1m 1 2 d5 led r26 4.7k lad[3:0] r21 10k 1 2 r29 1m sca_vcc scac8 pme# + c10 1u msled scac4 sd4 sd5 5vcc sdled u1 W83L518D_sb (lpc) 11 10 9 6 8 7 5 4 45 3 2 12 40 42 1 48 47 46 44 43 39 41 13 14 15 16 17 18 19 20 22 23 24 21 25 30 26 27 28 29 34 36 31 32 33 35 38 37 gp13 gp14 gp15 vss gp16 gp17 pme# lreset# lad2 lframe# ldrq# gp12 vdd3v sd4 pciclk serirq lad0 lad1 lad3 sd5 sd2 sd3 gp11/ex_cd gp10/hefras vdd scled scpwctl# scpsnt scclk scio xout xin ms5 scrst# ms4 vss ms3 ms2 ms1 msclk scc4 sdpwctl# mspwctl# msled scc8 sdled sd1 sdclk r30 1k sd_3vcc ex_cd scac4 d4 led ms5 r14 10 1 2 mspwctl# scaled scaclk hefras u2 48mhz 7 8 14 gnd out vcc r31 4.7k 1 2 ms1 lad0 r27 20k 1 2 soft start to protect mosfet(optional) 3vcc sd_3vcc q4 mosfet p c5 10p xin serirq 5vcc pcirst# c6 4.7u 1 2 sca_vcc lad2 inbond winbond electronics corp. scaio sd socket (1) circuit. sdclk ex_cd q3 mosfet p s1 sw spdt 2 1 3 scapsnt r12 10 1 2 r17 10 1 2 sd_3vcc sd2 W83L518D recommend circuit 0.4 b 2 2 tuesday, february 26, 2002 title size document number rev date: sheet of r25 1k 1 2 sc socket (1) circuit. sca_vcc sdpwctl# sdpwctl# lad1 ms3 r18 33 1 2 r24 330 scaled sca_vcc c9 0.1u 1 2 scac8 scarst# soft start to protect mosfet(optional) sd3 sdclk c4 10p msclk lframe# scaio ms2 pciclk 3vcc r28 10k
W83L518D the trademarks and intellectual property rights of memory stick belong to sony corporation publication release date: jul. .2002 the trademarks and intellectual property rights of sd belong to sd group revision 1.0 all trademarks and brand names belong to their respective owners 23 t he W83L518D schematic ms2 r1 330 1 2 r_jp1,2: 1x10 ; 2.0 mm(pitch) sd1 sdclk scaclk <> 3vcc (1)modified some erroneous netname like scpwr#,mspwr# and sdpwr#. (r_jp2) sdled scapsnt r2 33 1 2 r_j1 : 2x5 ; 2.54 mm(pitch) sd4 note 7: scac8 sd3 r3 4.7k sd4 mspwctl# msclk ms5 (option:reserved for power-down) (2)modified pull-down resistor tied to sd1 from 200k ohm to 1m ohm. the reset# should be connected with a low asserted signal like pcirst# on pci bus or lrest#on lpc bus(active low) scaled jp3 header 5x2 1 6 2 7 3 8 4 9 5 10 ms read/write led jp1 1 2 3 4 5 6 7 8 9 10 sd2 scac4 scapwctl# scaled winbond recommended reader board sd5 r4 330 if jp1,2,3,4 are designed for winbond recommended reader please meet following connector spec. (2)dma transaction cannot be supported in this version. ms_3vcc 3vcc scaio ms4 scapsnt msled memory stick socket (1) circuit. ms3 sdpwctl# scaio sd2 ms5 r6 1k 1 2 pin 1 pin 6 (3)added configuration port selection pin(gp10/hefras) by power-on strapping. ms4 sd4 jp3: 2x5 ;pitch(2.54mm) extension connectors ms1 r11 1m 1 2 pin 1 sd1 ms1 r7 1m 1 2 scapsnt note 6: scac8 sd3 r8 1m 1 2 r9 1m 1 2 msled c1 0.1u 1 2 (ver 0.3 --> ver 0.4) ms1 (2)modified pulled-high resistor for write_protect detection from 500 ohm to 4.7k ohm. sd5 note 5: ms_3vcc mspwctl# sdled jp1,2: 1x10;pitch(2.0mm) (1)added circuit(gp10/ex-cd)to implement to sockets with external card detection pin. soft start to protect mosfet(optional) (ver 0.2 --> ver 0.3) ms1 the trade marks and intellectual property rights of memory stick belong to sony corporation.information check: http://www.memorystick.org (r_j1) 3vcc 3vcc d1 led ms5 c3 0.1u (r_jp1) (1)added power-on strapping circuit of different configuration port.(2e/2f) q1 mosfet p pin 10 if any of sc or ms/sd function isn't intened to use, signals like scpsnt/scbpsnt should be tied to a pull-down resistor and ms[5:2]/sd[5:2] to pull-high resistors.these will reduce power consumption. (recommended: 4.7k-8.2k ohm ) there is either function of sd and ms can be used on versio a but two sockets interface can be implemented on version b. ms2 2 msa_3vcc note 4: ms2 mspwctl# ms3 scapwctl# r10 1m 1 2 (ver 0.1 --> ver 0.2) note 2: sdpwctl# r5 200k 1 2 pin 10 scaclk scarst# pin 1 inbond winbond electronics corp. scarst# note 1: msled scac4 ms4 + c2 1u msclk j1 ms_socket 1 2 3 4 5 6 7 8 9 10 jp2 1 2 3 4 5 6 7 8 9 10 there are some difference as following from previous version: 5vcc ms4 q2 npn 3vcc sd1 note 3: W83L518D recommend circuit 0.4 b 1 2 tuesday, february 26, 2002 title size document number rev date: sheet of sdclk ms3 d2 led 10 5 3vcc msclk for the recommended reader, please contact to taiwan zetatronic industrial co.,ltd(http://www.tzt.com.tw)

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